Edge AI for Firmware Engineers: Why It Matters and How to Start
A firmware-first guide to Edge AI: why inference is moving closer to sensors, what embedded engineers need to know, and how to validate an AI model on real hardware.
Blogs
A Practical Bare-Metal Secure Boot Kit for Cortex-M (A/B + Anti‑Rollback + QEMU Demo)
TL;DR: Want a secure‑boot example you can run, break, and verify (not just read)? This kit gives you a clean baseline: A/B slot boot, watchdog rollback, anti‑rollback, key lifecycle, and deterministic pass/fail demos on host + QEMU. Bare-metal secure boot you can actually run (and break) in 10 minutes Secure boot on Cortex‑M is not a service. It’s a single decision point immediately after reset: ✅ verify the candidate firmware image (format + integrity + “auth” binding) ✅ decide run or refuse to run ✅ behave deterministically under failure (no “crash and hope”) Most posts explain the idea. This one stays educational and gives you a runnable baseline you can reuse. ...
Reverse Engineering Firmware at Scale with IDA Pro
A practical, artifact-first approach to reverse engineering firmware with IDA Pro and IDAPython, combining manual analysis with repeatable automation workflows.
SW/HW CoSim That Sticks: Three Re-useable Practical Patterns
A practical comparison of three reusable SW/HW co-simulation patterns—file-based vendor TB flow, Verilator + C++, and cocotb + Verilator—using the same ready/valid DUT and repeatable verification artifacts.
SW/HW Co-Simulation Stack Design
A practical RISC-V SW/HW co-simulation stack that combines Unicorn ISS, a QuestaSim SystemVerilog testbench, and a DPI-C bridge for realistic pre-silicon firmware and RTL co-verification.
FPGA Prototyping in HLS C++ (Part 2)
In this blog, I delve into the core features and fundamentals of HLS C++, using Microchip SmartHLS as an example, including SW/HW co-simulation, custom C++ libraries, and basic SmartHLS pragmas.
FPGA Prototyping in HLS C++ (Part 3)
In this post, I discuss the HLS application development lifecycle using the RGB2YCbCr project as an example, and compare the HDL approach with the SmartHLS C++ approach for FPGA prototyping.
FPGA Prototyping in HLS C++ (Part 1)
In this blog, I introduce Microchip SmartHLS as an example to explain what high-level synthesis is, why it is useful, how HLS works internally, and how to write SmartHLS C/C++ code.
A Deep Dive into the CPU Usage Calculation on Linux
A deep dive into CPU load vs CPU usage on Linux, how CPU usage is used for performance and real-time feasibility analysis, and how to calculate it with vmstat, /proc/stat, and top.
How to write power-efficient code on powerless microcontrollers
A practical discussion of energy consumption on low-power microcontrollers and common coding and system-design techniques to minimize power usage in IoT firmware.